uvm - verification using Questasim -


i trying verify design in questasim , design in vhdl. using makefile. command 

vcom -93 -work $(work) $(rtl) $(svtb1) $(svtb)

it invoking vhdl compiler, not displaying master_driver signals.
can tell solution?

i got 1 solution don't know whether it's perfect one. solution question divide sv , vhdl codes in 2 different folders , compile them separately. work folder should same.


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