fpga - Mutiple VHDL files in a Lattice Diamond project -


i have fpga project multiple vhdl files (all compile no errors), written in lattice's diamond software. problem when go assign pins see inputs , outputs of 1 vhdl file. if delete file, see another, netlist analyzer has same behavior.

is possible have multiple vhdl files within same project or must write in 1 vhdl file?

a hardware description language describes design hierarchy. each design unit, component or module stored in separate hdl file. in case in different vhdl files. top vhdl design unit (entity) called top-level of hierarchy. file's ports can assigned device pins. other ports of subordinate design units must assigned port maps in instantiations.

it's not fault nor error of tool. should again building design hierarchies , how instantiate entities or components.


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