Vivado & Verilog: How to Use A Clock -

how use clock in verilog vivado?

i've tried no avail.

my project target artix-7 chip on arty artix-7 development board.

from i've gathered online, ip integrator i'm supposed use... nobody has decent introduction using it.

i've created design , created "clocking wizard," leaving every setting @ default [for now] (including input frequency being "auto").

then, in project manager, seems need tell design "create hdl wrapper." however, complains input clock pin not begin connected.

but that's point: i'm trying access clock source. don't have clock. can't figure out how clock. google failing me.

many google results have things nets , pins, if try declare variable

net clock_out1 ; // clock output design 

it complains net unrecognized. assume design has turned hdl wrapper need use resultant module same way use other module, can't figure out how make work.

how clock source?