Byte in x86 intel assembly padded with NOPs? -


when working single bytes, should 4 byte alignment taken account?

intel x86 pseudocode. @ beginning of 4096 byte page:

pageaddress:     01     nop nop nop <- 3 nops necessary?     cmp byte ptr [pageaddress], 01     je address     ...

the cmp byte ptr [pageaddress], 01 instruction deals 1 byte @ pageaddress. doesn't matter subsequent bytes filled with. fact these nops not impact cmp instruction.

  • dwords in memory should start @ 4-byte aligned addresses.
  • words mis-aligned when cross such 4-byte aligned border.
  • bytes can never mis-aligned.

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