How to use "hierarchical path" of chisel/scala? -

in verilog there such way access other module's stuff, know called "hierarchical path", here verilog rtl

module a;   reg a; endmodule module tb;   u_a();   wire b;   assign b = u_a.a; // hierarchical path endmodule  

could enlight me how access reg/wire of other modules in chisel/scala?

afaik, not possible in chisel3. if try error

an exception or error caused run abort: connection between sink (chisel3.core.uint@b) , source (chisel3.core.uint@1b) failed @: source unreadable current module.  chisel3.internal.chiselexception: connection between sink (chisel3.core.uint@b) , source (chisel3.core.uint@1b) failed @: source unreadable current module 

if want expose outside modules should through io mechanism. being said possible create syntactic appearance of direct access module using experimental feature multiiomodule

import chisel3._ import chisel3.experimental._  class extends multiiomodule {   val reg = reg(uint(16.w))   val r = io(output(reg))   r := reg }  class b extends multiiomodule {   val u_a = module(new a)   val b = wire(uint(16.w))   b := u_a.r }